This invention relates to the fabrication of semiconductor devices, and, more particularly, to a selective area process utilizing multiple steps of ion implantation and annealing to optimize the defect structure and dopant distribution in semiconductor wafers.
The advantage of utilizing a composite substrate having a single crystal semiconductor layer, such as silicon, epitaxially deposited on a supporting insulator substrate, are well-recognized in the field of semiconductor devices and integrated circuits. These advantages include the substantial reduction of parasitic capacitances between charged active regions and the substrate, and the effective elimination of leakage currents flowing between adjacent active devices. These advantages are accomplished by employing as the substrate an insulator material with a high dielectric constant, and providing that the conduction path of any interdevice leakage current must pass through the substrate. Examples of such materials include silicon on calcium fluoride, silicon on silica, silicon on spinel, silicon on sapphire, and silicon on zirconia.
Because of the very small dimensions involved in such devices, which may be on the order of tenths of micrometers, the concentrations and gradients of defects and dopant species in the silicon are critical to the operation of the active devices fabricated thereupon. For many active devices, it would be desirable that the silicon layer be completely single crystal and substantially defect free in the necessary thickness. The interface between the silicon layer and the supporting insulator substrate should have a minimum of crystal lattice discontinuities. On the other hand, it is desirable in many instances, for certain applications and types of active devices fabricated on the silicon, that the defect and dopant structures be individually tailored and optimized.
Attempts to achieve optimized defect and dopant structures face significant obstacles due to the need to anneal the wafers at high temperatures to reduce the defect concentration, and the dissolution of dopant species from the insulator substrate into the silicon at such high temperatures. That is, the necessary high-temperature annealing treatment to minimize the silicon defect concentration also may result in a high concentration of the insulator species, such as aluminum ions, in the silicon. While the introduction of aluminum dopant into the silicon may be desirable in some instances, it is sufficient to render other active devices inoperable.
By way of a response to this problem, a number of implantation and specialized annealing processes have been developed. In particular, techniques have been developed to reduce the defect concentration in the silicon layer without resorting to high temperature annealing. One such process, known as solid phase epitaxy, or SPE, provides a low temperature subprocess for improving the crystallinity of the silicon epitaxial layer without heating the wafer to temperatures greater than about 600.degree. C. The SPE process involves the high energy implantation of an ion species such as silicon into the silicon epitaxial layer at a dose sufficient to create a substantially amorphous silicon layer lying adjacent the silicon-insulator interface, while leaving a substantially crystalline layer at the surface of the original epitaxial silicon layer. The ion species is implanted below the top layer of the epitaxial silicon layer so that the maximum disruption of the silicon crystal lattice is in a buried layer near the silicon-sapphire interface to ensure that the amorphous region is adjacent the sapphire substrate. The wafer is then given a low temperature annealing treatment to achieve an epitaxial recrystallization of the buried amorphized silicon layer. With this process, the silicon surface layer remains partly disrupted due to the ion implantation, and the buried near-interface silicon layer is recrystallized into a structure having a lower density of crystalline defects.
While the solid phase epitaxy process does significantly improve the crystallinity of the silicon epitaxial layer, it also facilitates the incursion of insulator-originated contaminants into the silicon epitaxial layer. For example, if the substrate is sapphire, aluminum species can migrate into the silicon layer, thereby contaminating the layer and effectively precluding the practical use of integrated circuits fabricated on contaminated substrates so processed.
Therefore, there exists a continuing need for a process for controlling and optimizing the defect and dopant concentrations in silicon-on-insulator wafers to be used in fabricating active semiconductor devices thereupon. Such a process would ideally allow the preparation of a substantially defect-free silicon single crystal on the insulating substrate, while at the same time either utilizing or compensating for the effect of the incursion of substrate-originated contaminants that diffuse into the silicon layer. The process also should be fully compatible and integratable with existing conventional semiconductor device and integrated circuit fabrication technology. The present invention fulfills this need, and further provides related advantages.